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IGNOU MCS 202 Solved Assignment 2024
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Rs. 50

IGNOU MCS 202 Computer Organisation Solved Assignment 2024

IGNOU MCS 202 Computer Organisation Solved Assignment 2024
Rs.
Rs. 50

Last Date of Submission of IGNOU MCS-202 (PGDCA_NEW) 2024 Assignment is for January 2024 Session: 30th September, 2024 (for December 2024 Term End Exam).
Semester Wise
January 2024 Session:
30th March, 2024 (for June 2024 Term End Exam).
July 2024 Session: 30th September, 2024 (for December 2024 Term End Exam).

Title Nameignou MCS 202 solved 2024
TypeSoft Copy (E-Assignment) .pdf
UniversityIGNOU
DegreePG DIPLOMA PROGRAMMES
Course CodePGDCA_NEW
Course NamePOST GRADUATE DIPLOMA IN COMPUTER APPLICATIONS
Subject CodeMCS 202
Subject NameComputer Organisation
Year2024
Session-
LanguageEnglish Medium
Assignment CodeMCS-202/Assignmentt-1//2024
Product DescriptionAssignment of PGDCA_NEW (POST GRADUATE DIPLOMA IN COMPUTER APPLICATIONS) 2024. Latest MCS 202 2024 Solved Assignment Solutions
Last Date of IGNOU Assignment Submission
Last Date of Submission of IGNOU MCS-202 (PGDCA_NEW) 2024 Assignment is for January 2024 Session: 30th September, 2024 (for December 2024 Term End Exam).
Semester Wise
January 2024 Session:
30th March, 2024 (for June 2024 Term End Exam).
July 2024 Session: 30th September, 2024 (for December 2024 Term End Exam).

Assignment CodeMCS 202/2024
Rs.
Rs. 50
Questions Included in this Help Book

Ques 1.

Explain the von Neumann architecture. Show how an instruction is executed by the von Neumann machine.

Ques 2.

Explain the main architectural differences between the von Neumann architecture and Harvard architecture with the help of a diagram of each.

Ques 3.

Perform the following conversion of numbers:

Ques 4.

Decimal (2536475891)10 to binary and hexadecimal.

Ques 5.

Hexadecimal (FABCD1E)h to Octal

Ques 6.

String “ISO-8859-1 coding” to UTF 16.

Ques 7.

Octal (23174560)O to Decimal

Ques 8.

Simplify the following function using K-map: F(A, B, C, D) = Σ (1, 3, 5, 7, 8, 12, 14, 15). Draw the circuit of the simplified function using NAND gates.

Ques 9.

Consider the Adder-Subtractor circuit given in Unit 3 of Block 1. Explain how this circuit will perform subtraction (A-B) if the value of A is 1010 and B is 1011. You must list all the bit values, including Cin and Cout and overflow condition

Ques 10.

Explain the functioning of a 38 decoder. You should draw its truth table and explain its logic diagram with the help of an example input

Ques 11.

Assume that a source data value 1001 was received at a destination as 1101. Show how Hamming's Error-Correcting code will be appended to source data so this error of one bit is identified and corrected at the destination. You may assume that the transmission error occurs in the source data, not the error correction code.

Ques 12.

Explain the functioning of the SR flip-flop with the help of a logic diagram and characteristic table. Also, make and explain the excitation table of this flip-flop.

Ques 13.

Explain the functioning of a 3-bit ripple counter with the help of a diagram

Ques 14.

Represent (-55.25)10 and (0.03125)10 in IEEE 754 single precision format.

Ques 15.

Explain the logic structure of SRAM and DRAM cells. How many RAM chips of size 256K  8 bits are needed to build a memory of size 16M Word RAM having a word size of 32 bits? Find the storage capacity of a disk with 16 recording surfaces and 32 tracks; each track has 64 sectors. You may

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Rs. 50

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